Added Verilog

2014-11-25 21:06:25 -03:00
parent 4691aea289
commit 039c3a0982
1 changed files with 7 additions and 0 deletions
--- a/v/verilog.v
+++ b/v/verilog.v
@@ -0,0 +1,7 @@
+module main;
+  initial
+    begin
+      $display("Hello World!");
+      $finish;
+    end
+endmodule