Merge pull request #157 from fulano7/master

Added Verilog
2015-04-12 13:33:09 -04:00
parent 2f8981e95c 039c3a0982
commit cd3fe66374
1 changed files with 7 additions and 0 deletions
--- a/v/verilog.v
+++ b/v/verilog.v
@@ -0,0 +1,7 @@
 module main;
  initial
    begin
      $display("Hello World!");
      $finish;
    end
 endmodule